1. Field of the Invention
The invention relates in general to a package structure, and more particularly to a flip chip package structure.
2. Description of the Related Art
In the past few years, electronic products are developing toward being thin and small, multi-functioned, and high-speed, semiconductor package structures with high density and high output/input are more and more required, so the flip chip package process is increasingly applied instead of the wire bond package process and the tape automated bonding (TAB) package process. The flip chip package process can not only have good electrical features by using less interface bonding paths, but also achieve the requirement of multi-input/output pins since the designer can utilize the space of the chip more effectively.
Referring to FIG. 1, a lateral diagram of the conventional flip chip package structure is shown. Several solder bumps 104, disposed on the front surface 102a of the chip 102 are formed as bonding joints to electrically couple the chip 102 with the substrate in the solder reflow process. Moreover, solder balls 108 are disposed on the lower surface 106b of the substrate 106 for electrically coupling the package structure 100 with the exterior circuits. Underfill materials 110, filled in the region between the chip 102 and the substrate 106 in the underfill process, cover and sustain the solder bumps 104 to improve the bonding strength of the chip 102 and the substrate 106.
In addition, in order to maintain a good operation of the flip chip package structure, a heat sink is provided for releasing heat generated from the chip to the exterior. As shown in FIG. 1, a metal ring 112, encircling the chip 102, is disposed on the upper surface 106a of the substrate 106 for raising the heat sink 114 up, so that the heat sink 114 can be heat-conductively coupled to the back surface 102b of the chip 102. Furthermore, the heat sink 114 can be attached to the back surface 102b of the chip 102 and the upper surface of the metal ring 112 through the adhesion of the thermal interface material (TIM) 116.
Although the underfill technology used in the flip chip package process can solve the issue that bonding joints are damaged by the expanding stress when hot and the shrinking stress when cold, the facts that the flowing time of the underfill materials is difficult to control and the time for underfill material solidification is too long reduce production performance and further lead to a bottleneck of the manufacturing process.